Digital line driver circuit

ABSTRACT

A digital line driver circuit  1  for driving a transmission line and being arranged to receive a digital input signal Di and output a digital output signal in accordance with said digital input signal Di, said digital line driver circuit being operable in at least a first and a second mode in accordance with a mode selection signal Pe, wherein said first mode is a signal relay mode in which said digital output signal follows said digital input signal, and said second mode is a pre-emphasis mode in which said digital output signal follows said digital input signal and has an additional predetermined distortion.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a digital line driver circuitfor driving a transmission line, and to a method of operating a digitalline driver circuit.

[0002] It is well known that when transmitting a signal over a frequencydependent medium like a real transmission line having frequency lossesor over an optical cable, the signal shape will change in the course ofthe transmission. A bandwidth limited electrical transmission line willfor example cause higher losses in high frequency components of atransmitted signal than in lower frequency components. The effect of thetransmission medium on the signal is the more pronounced the higher thefrequency components of the signal to be transmitted is, and the longerthe transmission length through the medium is. This effect imposeslimits on the maximum transmission length and/or the maximum speed of asignal transmission system having a signal driver at an input side ofthe transmission medium and a receiver for receiving signal outputs bythe transmission medium at the other side.

[0003] Modern communication systems use digital signals for carryinginformation. Generally speaking, a digital signal generally consists ofa random sequence of so-called symbols, each representing one or moredata bits. When a digital signal is transmitted over a frequencydependent medium like a transmission line, the transmitted digitalsignal will suffer from the distortion even if there is perfect matchingat the receiver side and at the transmitter side, because the higherorder harmonics in the signal spectrum suffer from higher losses thanlower frequency components of the signal spectrum. Shorter pulses in thedigital signal at the receiver side will not reach their full amplitudeand the slope of the rising and falling edges in the signal seen by thereceiver will deteriorate. This effect, also called inter symbolinterference (ISI) imposes limits on the data rate that the receiverwill be able to detect.

[0004] It is known to increase the limits of the data rate or thetransmission length over a given medium by means of pre-distorting thedigital signal at the input side of the medium. Broadly speaking, thepre-distortion takes into account the distortion caused by thetransmission medium, by means of emphasizing components of the signal tobe transmitted that will suffer from loss in the transmission medium.This technique is also known as pre-emphasis.

[0005] As disclosed e.g. in DE 198 25 256, a conventional way to providea digital data signal with pre-distortion or pre-emphasis is to delaythe digital signal by one bit period or a predetermined fraction of thebit period and to combine the amplitude of the digital signal and thedelayed digital signal. From this document an output buffer circuit isknown that is able to provide a digital output signal withpre-distortion by means of determining the output signal level dependingnot only on the current data bit to be transmitted, but also dependenton the history of the output signal.

[0006] U.S. Pat. No. 4,5584,690 discloses minimizing the effect of intersymbol interference by provision of digital pre-compensation in thetransmitted signal, in order to maximize the slew rate betweenconsecutive bits. From this document, it is known to base thepre-compensation scheme on knowledge of the bit pattern and the amountof energy contained in a sequence of bits.

[0007] From IEEE Journal of Solid State Circuits, volume 34, no. 5, May1999, pages 580 to 585 a so-called full bit pre-distortion combines theamplitudes of the digital data signal with the weighted amplitudes ofone or more delayed versions of the digital data signal, each delayedversion having a delay of one or more full bit periods relative to theundelayed digital data signal. The number of delayed versions of thedigital data signal with different delay that are combined togetherdetermine the so-called order of pre-distortion. It is known from thisdocument that partial bit pre-distortion is equally well feasible bymeans of combining the digital data signal with a delayed version of it,the delay being set to p times to bit period. The typical value of p is0,5, this being called half bit pre-distortion.

[0008] It is to be noted that the term “bit” in this context does notnecessarily mean a unit of information or a data unit. Rather, in thecontext of pre-distortion or pre-emphasis this term generally refers toa repetitively at random occurring constant amplitude segment of minimumduration in the digital data signal. In the special case that thedigital data signal format is binary providing two symbols representedby two different signals, one representing logical “0” and the otherlevel representing logic “1”, then a segment of minimum duration havethe same duration as a bit period. There exist, however, other wellknown digital signal formats wherein a segment of minimum duration has aduration different from the duration of an information bit.

OBJECT OF THE INVENTION

[0009] It is the object of the present invention to provide an improveddriver circuit for outputting digital signals to a transmission line,where said driver circuit provides pre-emphasis capabilities. It is alsoan object to provide an improved method of operating such a digital linedriver circuit.

SUMMARY OF THE INVENTION

[0010] These objects are achieved by a digital line driver circuit asdescribed in claim 1, and by a method of operating a digital line drivercircuit as described in claim 14. Advantageous embodiments are describedin the dependent claims.

[0011] In accordance with the present invention a digital line drivercircuit is provided that receives a digital input signal and outputs adigital output signal in accordance with said input signal, where thedigital line driver circuit is operable in at least a first and a secondmode. The respective mode is determined by a mode selection signal. In afirst mode no pre-emphasis is added to the output signal. The first modecan, for example, be a signal relay mode in which the digital outputsignal follows the digital input signal. The second mode is apre-emphasis mode, in which the digital output signal follows thedigital input signal, but has an additional pre-distortion.

[0012] Therefore, the digital line driver circuit of the presentinvention can deliver both signals with and without preemphasis. Anormal signal may simply replicate or directly follow the input signal,whereas a pre-emphasis signal has added distortion. Therefore, thecircuit of the present invention provides the advantage of pre-emphasisif necessary for the specific signal being transmitted or the specificprevailing conditions, but is not restricted thereto, and can alsooutput a normal signal if this is necessary or desired. The presentinvention therefore provides great flexibility.

[0013] The digital line driver circuit comprises a signal processingsection and an output stage, where the signal processing sectionreceives the digital input signal and outputs control signals to theoutput stage. Preferably, the signal processing section contains a delaycircuit in order to generate appropriate control signals for thepre-emphasis mode. The use of delays for generating pre-emphasis signalsis well known, as mentioned in the introduction. However, it may benoted that the control signals for the pre-emphasis mode may begenerated in any suitable or appropriate way. The documents mentioned inthe introduction to the specification are herewith incorporated byreference.

[0014] The output stage is preferably arranged to have an outputimpedance matched with the transmission medium, e.g. 50 Ohm, for bothdifferential and common mode transmission. Also it is advantageous toprovide an internal supply current balancing mechanism that is able tocancel the internal data signal dependent current load variations. Thiscurrent load balancing mechanism is arranged to work over a large commonmode range. It alleviates the need for internal power supplies with lowoutput impedance and reduces the switching transient load such thatdecoupling capacitors, if any, between the internal power supply linesand ground can be kept small.

[0015] The output stage can be arranged to be fed from external powersources, where the number of external power sources can be equal to thenumber of levels provided in the signals of the pre-emphasis mode.However, it is equally possible to also provide the output stage with alesser number of external reference voltages, in which case the outputcircuits itself may generate appropriate reference voltages e.g. withvoltage dividers. The latter alternative has the advantage of reducingthe number of external components and complexity.

BRIEF DESCRIPTION OF FIGURES

[0016] The present invention will know be described in more detail withreference to a number of preferred embodiments, which are intended toconvey a more complete understanding of the invention, but are not to beunderstood as restricting the invention, and with reference to theenclosed drawings, in which:

[0017]FIG. 1 shows a basic embodiment of the present invention,

[0018]FIG. 2 shows a detailed example of the embodiment of FIG.

[0019]FIG. 3 shows logic state diagrams of a plurality of signals thatappear in the circuit of FIG. 2,

[0020]FIG. 4 shows a preferred embodiment of a signal generating sectionand a signal switching section in an output stage,

[0021]FIG. 5a and 5 b show circuit diagrams explaining the operation ofan output stage provided with current load balancing,

[0022]FIG. 6a and 6 b show examples of a current balancing section usingMOS technology, and

[0023]FIG. 7a and 7 b show examples of a signal switching section usingMOS technology.

DETAILED DESCRIPTION OF INVENTION

[0024] In the following description the same reference numerals shall beused for describing the same or equivalent elements throughout all ofthe figures.

[0025]FIG. 1 shows a preferred embodiment of the present invention.Reference numeral 1 describes a digital line driver circuit. Referencenumeral 2 describes a signal processing section that receives a digitalinput signal Di and a mode selection signal Pe. The signal processingsection 2 is arranged to output one or more control signals S2. Thesecontrol signals S2 are provided to an output stage 3, which in turnproduces output signals OUTP and OUTN for an output line 4 being drivenby the digital driver circuit 1. In accordance with the presentinvention the signal processing section 2 produces control signals S2 inaccordance with a first mode and a second mode, where the first mode isa normal mode, in which the output signal follows the input signal Di,and the second mode is a pre-emphasis mode, in which distortion orpre-emphasis is added. The operation mode is determined by the modeselection signal Pe, which e.g. can simply have two levels where thefirst level corresponds to the first mode and the second level to thesecond mode. It should, however, be noted that the circuit 1 of thepresent invention can also operate in accordance with more than twomodes, in which case the mode selection signal Pe will be able toindicate the individual modes appropriately, e.g. by a plurality oflevels, or by any other suitable coding mechanism.

[0026]FIG. 2 shows a detailed example of the circuit of FIG. 1. In FIG.2 the signal processing section 2 receives the digital input signal Diand the inverse Dib of the digital input signal Di. It may be noted thatthe inverse signal Dib can be provided from the outside, or couldequally be provided by an appropriate inverter (not shown) in the signalprocessing section 2. The signal processing section 2 furthermorecomprises a delay circuit 21 that provides a delay ΔT to signals inputto said delay circuit 21. Both signals Di and Dib are fed to the delaycircuit 21, in order to output corresponding delayed output signals Dd(corresponding to Di) and Ddb (corresponding to Dib).

[0027] The signal processing section furthermore comprises an input forthe mode selection signal Pe, which is fed to an inverter 22.Furthermore, the signal processing section 2 comprises OR gates 23 and27, as well as AND gates 24, 25, 26, 28, 29 and 30. These gates form agate section for receiving and processing the input signals Di, Dib andPe, and the delayed signals Dd, Ddb and the inverted mode selectionsignal.

[0028] More specifically, gate 23 receives the delayed inverted signalDdb and the inverted mode selection signal, and gate 24 receives theoutput from gate 23 and the input signal Di. Gate 24 outputs a controlsignal A. Gate 25 receives the delayed signal Dd and the mode selectionsignal Pe. Gate 26 receives the output from gate 25 and the input signalDi. Gate 26 outputs a control signal B. Gate 27 receives the invertedmode selection signal and the delayed signal Dd. Gate 28 receives theoutput from gate 27 and the inverted input signal Dib. Gate 28 outputs acontrol signal C. Gate 29 receives the mode selection signal Pe and thesignal Ddb. Gate 30 receives the output from gate 29 and the invertedinput signal Dib. Gate 30 outputs a control signal D.

[0029] The control signals A, B, C and D are provided to output stage 3and correspond to the signals S2 shown in FIG. 1. The different statesassociated with the various signals will be described further on inconnection with FIG. 3.

[0030] The output stage 3 is shown as receiving four reference voltagesVrph, Vrrh, Vrrl and Vrpl. Vrph is the peak high reference voltage andVrpl is the peak low reference voltage, e.g. ground in the case of GLVDSor a somewhat higher level in case of LVDS. Vrrh and Vrrl areintermediate or relaxed voltages that have a value between Vrph andVrpl. As already mentioned previously, it is not necessary to providethe four shown reference voltages to the output stage 3 and it woulde.g. also be sufficient to only provide the peak high reference voltageVrph and the peak low reference voltage Vrpl, and to arrange the outputstage 3 to appropriately generate the intermediate voltages Vrrh andVrrl.

[0031] The different logic states produced by the various signals willnow be explained in connection with FIG. 3. The mode selection signal Peindicates when the pre-emphasis logic is activated or disabled. When thepre-emphasis logic is disabled, the control signals A and C follow Diand Dib, and the two control signals B and D remain low. The outputstage 3 is arranged in such a way, that in this working mode only thatpart of the output stage 3 connected to high and low peak voltages Vph(generated in response to Vrph) and Vpl (generated in response to Vrpl)is active. There are only two “states” used in this working mode, A andC. This is shown on the right hand side of FIG. 3. As can be seen, theoutput from the output stage 3 exactly follows the input signal Di. Thisis the normal mode.

[0032] On the other hand, as shown on the left hand side of FIG. 3, whenthe mode selection signal Pe is high, then the pre-emphasis logic isactive, and four “states”, A, B, C and D occur, which allow the outputstage to produce a signal which allows the output stage to produce asignal with pre-distortion or pre-emphasis having four levels,corresponding to the four active control signals A, B, C and D.

[0033] In a general sense, when the input signal has n levels, n beingan integer, such that the normal mode output signal also has n levels,and the pre-emphasis mode output signal has m levels, m being an integerlarger than n, then the signal processing circuit will preferably bearranged to provide n active control signals to the output stage in thenormal mode and m active control signals in the pre-emphasis mode, andthe output stage will be arranged to generate an n level output signalin the normal mode and an m level signal in the pre-emphasis mode.

[0034] The time delay ΔT determines the length of the pre-emphasispulse, i.e. the short pulses seen in signals A and C on the left handside of FIG. 3, while Pe is high. This time delay ΔT can be as long asthe data bit itself, but it can also be shorter, as e.g. seen in FIG. 3,where it is half of a bit interval. As already mentioned previously, ingeneral the precise mechanism for generating pre-distortion can,however, be selected in any desired or suitable way known in the art.

[0035] In the example of FIGS. 2 and 3, the input signal Di was a twolevel signal, such that the output signal in the normal mode was also atwo level signal, and the output signal in the pre-emphasis mode was afour level signal. However, the invention is applicable in any system,where the input signal and normal mode output signal generally have nlevels, where n is an integer, and where the pre-emphasis mode outputsignal has m signal levels, where m is an integer larger than n.

[0036]FIG. 4 shows a preferred embodiment of the output stage 3. Theoutput stage 3 of FIG. 4 comprises a signal generating section 31 and asignal switching section 32. The signal generating section 31 isarranged to generate and output m signals corresponding to the number oflevels in the pre-emphasis mode, indicated as S32 in FIG. 4. Each ofthese signals S32 has its own distinctive level and an impedancesufficiently low for driving the transmission medium, e.g. adifferential transmission line. The signal switching section 32 isarranged to receive these m signals and to receive the control signalsS2 (or A, B, C, D) that were output by signal processing section 2. Thesignal switching section 3 is arranged to switch between the distinctivelevels of the m signals in order to generate and output signals OUTP andOUTN. As already explained in connection with FIG. 3, the signalswitching section 32 is arranged to only switch between n levels in thenormal mode, e.g. two levels in the example of FIG. 3, and between mlevels in the pre-emphasis mode, e.g. four in the example of FIG. 3.

[0037] The signal generating section 31 of FIG. 4 furthermore comprisesa reference voltage providing section 310 arranged to output a pluralityof reference voltages S31. In the example of FIG. 2, the referencevoltage providing section was simply constituted by the four inputs forthe four reference voltages Vrph, Vrrh, Vrrl and Vrpl. As alreadymentioned, it is also possible that the reference voltage providingsection contains circuits for generating or adjusting reference voltagesprovided from external sources. In general, the reference voltageproviding section 310 will output m voltage levels S31, corresponding tothe m levels of the pre-emphasis mode, where it may provide these mlevels on the basis of m or fewer external voltages.

[0038] In FIG. 4 the signal generating section 31 furthermore comprisesa signal source section 311 that contains a plurality of impedanceconversion devices and is arranged to receive the plurality of referencevoltages S31 and to generate m signals S32 in response thereto. Theimpedance conversion devices may simply be source followers or emitterfollowers. Advantageously, these devices are constituted to comprise apush pull output stage which is able to source currents as well as sinkcurrents in order to achieve proper source matching of the output to thetransmission medium.

[0039] It may be noted that although it is preferable that circuit 31operate on the basis of m reference voltages and m impedance convertersin section 311, where each impedance converter is responsible forproviding a signal having a distinctive voltage level associated withthe respective reference voltage, and m is the number of levels providedin the pre-emphasis mode, it is also possible that a different number ofreference voltages is provided and that fewer impedance converters areemployed. Namely, one appropriately arranged impedance converter couldalso be operated to switch between a plurality of output signals S32. Inthis case the control signals S2 would also be provided to circuit 311,as indicated by the dashed arrow in FIG. 4.

[0040] As an option, the circuit of FIG. 4 furthermore comprises acurrent balancing section 312 arranged to balance the supply currentsdrawn by the plurality of impedance converters in signal source section311. The dashed arrow carrying control signals S2 also indicates thatwhen providing the current balancing section 312 in conjunction with thesignal source section 311 it is preferable to also control the currentbalancing section 312 in accordance with the same control signals S2that control the operation of signal switching section 32. In this wayit is possible to reduce spurious noise coupling into other circuits viathe power supply rails.

[0041] The current balancing section 312 preferably comprises aplurality of switching devices that are controlled in dependence on thecontrol signals S2 and are arranged to selectively provide connectionsbetween predetermined outputs of the impedance converters provided inthe signal source section 311. These connections have predeterminedimpedance values.

[0042] The operation of the circuit shown in FIG. 4 shall be explainedin more detail with reference to an example thereof shown in FIG. 5a. Onthe left hand side of FIG. 5a, terminals for the high peak referencevoltage Vrph and the low peak reference voltage Vrpl are shown. In theexample of FIG. 5a, these are the only reference voltages supplied fromexternal sources. The intermediate or relaxed voltages Vrrh and Vrrl areprovided by means of dividing resistors Rrp, Rrr. In the example of FIG.5a, Rrp has a resistance value R and Rrr has a resistance value 2R. Ingeneral, these values may naturally be chosen as is suitable ornecessary.

[0043] In FIG. 5a operational amplifiers Aph, Arh, Arl and Apl arearranged to be impedance converters 3111, 3112, 3113, 3114 in the signalsource section. The impedance converters 3111-3114 receive respectivereference voltages Vrph, Vrrh, Vrrl and Vrpl at their non-invertinginputs. The amplifier output is fed back to the inverting input, suchthat the amplifiers act as low impedance sources for outputting signalsat respective voltage levels Vph, Vrh, Vrl and Vpl.

[0044] The signals output by the low impedance sources 3111-3114 areprovided to the output of the output stage via the signal switchingsection 32, which comprises switching elements 3211-3218, where each ofsaid switching elements 3211-3218 is controlled in accordance with oneof the control signals A, B, C and D, and each has a suitable ONimpedance Rout which is preferably selected such that at any time thesum of all impedances connected in series through the transmissionmedium matches with the characteristic impedance of the transmissionmedium.

[0045] In the example of FIG. 5a, the switching elements 3211-3218 arearranged such that if the shown control signal A, B, C or D is high,then the respective switching element is conductive. In the figure,signal A is assumed to be high, such that switches 3211 and 3218 areconductive, whereas switches 3212, 3213, 3214, 3215, 3216 and 3217 areopen (non-conductive).

[0046] With this arrangement, the operation as shown in FIG. 3 can beprovided. Namely, in the normal mode, in which only control signals Aand C are active, only the high peak voltage Vph and the low peakvoltage Vpl are switched to the output line 4, in order to produce thetwo level output signal that strictly follows the two level inputsignal. On the other hand, during the pre-emphasis mode in which controlsignals A, B, C and D are active, four signal levels Vph, Vrh, Vrl andVpl are switched to the output line 4.

[0047]FIG. 5a furthermore shows switches 3121, 3122 and 3123 thattogether constitutes a current balancing section for balancing thesupply current drawn by the low impedance sources 3111 to 3114. Switch3121 is connected between the outputs of sources 3111 and 3112 and isconductive when signal B or D is high, and has an appropriate ONimpedance Rpr. Switch 3122 is connected between the outputs of sources3113 and 3114, is conductive if signal B or D is high, and has asuitable ON impedance Rpr. Switch 3123 is connected between the outputof source 3111 and source 3114, is conductive if control signals B or Dare high, and has a suitable ON impedance Rpp.

[0048]FIG. 5a shows an example where control signal A is high in whichcase the signal at the high peak level Vph is output via switches 3211and 3218, and the switching elements 3121 to 3123 of the currentbalancing section are open (non-conductive). FIG. 5b shows the situationwhen signal B is high, in which case the switches 3121 to 3123 of thecurrent balance section are closed and the switches 3213 and 3216 act toprovide signals of intermediate voltage level to the output in order togenerate an output signal having pre-distortion, i.e. having a largernumber of signal levels than the input signal.

[0049] More specifically, if one assumes Vrph as being 2 V above Vrpl,then the resistor ladder Rrp, Rrr, Rrp in the reference voltageproviding section provides intermediate voltages 1.5 V higher than Vrpland 0.5 V higher than Vrpl for Vrrh and Vrrl (i.e. with Rrp having aresistance value R and Rrr having a resistance value 2R). This voltagecombination gives a pre-emphasis grade of 100%. If all the impedancesRout of the switching elements 3211 to 3218 in the switching section areset to be 50 Ohm and the differential characteristic impedance of thetransmission line is 100 Ohm, then a proper differential source matchingis achieved. The differential voltage across OUTP, OUTN will then be 1Volt. The current through the load will be 10 mA, and the current issupplied from the two voltage supply amplifiers Aph and Apl, in thedirections as indicated by the arrows in FIG. 5a. The two amplifiers inthe middle will be active keeping their potentials Vrrh and Vrrl, butidling due to a lack of current load.

[0050] It may be noted that the situation for signal C being high isbasically equal to the situation shown in FIG. 5a, but with reversedoutput by the output switches.

[0051] In the situation of FIG. 5b, assuming the same parameters asdiscussed above in connection with FIG. 5a, the switches feed out therelaxed intermediate voltage levels of 1.5 and 0.5 V, which gives 0.5Volt across the output terminals OUTP, OUTN and a current of 5 mA. Inthis phase, all the balancing switches 3121 to 3123 are engaged orclosed. The upper and lower resistors 3121 and 3122 are dimensioned tofeed 5 mA to the load and thereby maintaining the idling of the supplyamplifiers 3112 and 3113 in the middle. The middle resistor 3123 isdimensioned to handle the remaining current, 5 mA, to keep the upper andlower supply amplifiers 3111 and 3114 under the same load condition of10 mA as in the situation described in connection with FIG. 5a.

[0052] It may be noted that the situation for signal D being high isbasically equal to the situation for signal B being high, but the outputis reversed by the output switches.

[0053] Accordingly, as long as the output stage is subjected to animpedance matched load, the current to and from the supply amplifiersAph, Arh, Arl, Apl will be constant due to the balancing devices suchthat noise coupling into other circuit sections via the power supplylines can be suppressed effectively.

[0054] If the load is not matched, or the termination mid point Vp atthe other end of the transmission line (see FIG. 5a) is forced in anydirection, there will be a modulation of the currents in the outputstages. This can lead to a deteriorated output signal if the supplyamplifiers have a too high output impedance or too slow response time.Accordingly, it is preferable to use low impedance source circuitshaving low output impedance and fast response time.

[0055] The dynamic response to fast variations like switching transientsin the supply voltages can be handled by suitably dimensioned decouplingcapacitors (not shown). DC up to signalling frequencies are handled bythe supply amplifiers and by the current balancing circuitry.

[0056]FIGS. 6a and 7 a show an implementation example of the outputstage shown in the previous figures. FIG. 6a shows an example of thecurrent balancing section, and FIG. 7a shows an example of the signalswitching section. In the FIGS. 6 and 7, NMOS devices are shown, whichare dimensioned to provide both the switching functionality and thecorrect ON impedance.

[0057] The supply lines Vrh, Vph, Vpl, Vrl shown in the currentbalancing section of FIG. 6a are shown in a slightly different orderthan in FIG. 5a, in order to make the drawing simpler. Also, in theexample of FIG. 6a, the functionality of the three switching elements3121 to 3123 shown in FIG. 5 is provided by 6 transistors, in order tomake the logic simpler and to maintain a uniform delay. Naturally, itwould also be possible to only provide three transistors or to providemore than 6 transistors. When using three transistors, the requiredresponse to either the signal B or the signal D can be implemented withan OR gate (see also FIG. 6b).

[0058] The signal switching section shown in FIG. 7a forms the 8 outputswitches 3211 to 3218 and their related output impedances Rout. Thesupply rails are grouped, the lower part is driven by the peak suppliesVph, Vpl, and the upper part is driven by the relaxed or intermediatesupplies Vrh, Vrl.

[0059] The dimensioning of the devices is dependent on the requiredoutput impedance, their internal source and drain potential and thesupply voltage controlling the gates of the devices.

[0060] The lower devices connected to ground or the lowest referencepotential can be smaller in size, because their gate to source voltagesare larger than in devices that are connected to a higher potential.Devices connected with drain and source to higher potential need to belarger due to a smaller gate to source voltage. These dimensions will beindividually chosen by a skilled person for a combination ofpre-emphasis grade and a desired output voltage, in accordance withindividual demands and desires.

[0061] In order to serve a number of different output voltages anddifferent pre-emphasis grades, it is preferable to provide a number ofdifferent dimensions for the same devices, in order to maintain thecorrect output impedance. This can be done by providing a number ofparallel output units, where each output unit can be individuallyselected in order to give a correct drive strength to the output. Thisis shown in FIGS. 6b and 7 b, where FIG. 6b shows a current balancingsection and FIG. 7b shows a signal switching section.

[0062] As can be seen in FIGS. 6b and 7 b, the appropriate parallelunits are arranged to receive a selection signal SEL1, SEL2, or SEL3 foractivating each respective unit. The selection signals are fed to ANDgates that also receive appropriate control signals A, B, C or D. Eachunit is arranged to provide a predetermined respective impedance to theoutput signal.

[0063] The units can either be unique for each operation mode with onlyone working unit per mode, or have one base stage size which workssimultaneously with none or a number of other small delta sized outputunits.

[0064] The latter solution saves both space and lowers outputcapacitance due to a smaller total area of the devices connected to theoutput lines. The different dimensioning is also important for thebalancing section, which also should be dimensioned for differentoperating points. The controlling of different drive strength andcurrents is shown in FIGS. 6b and 7 b, where the different parts can beselected by the selection signals SEL1, SEL2, SEL3 and AND gates, whichreceive the selection signals and respective control signals A, B, C orD.

[0065] It may be noted that in FIG. 6b the balancing section uses an ORgate instead of the dual rows of transistors shown in FIG. 6a.

[0066] Although the present invention has been explained in conjunctionwith specific embodiments, the invention is by no means restricted tothese specific embodiments, as many variations will occur to the personskilled in the art. For example, although the specific implementationexample above showed NMOS devices as driving devices, all of thesecircuits can naturally also be put to practice with PMOS devices orcombinations of NMOS and PMOS devices, depending on the requirements ofoutput voltages and supply voltages. The logic of the correspondingsignals, such as the control signals A-D and the mode selection signalPe must then accordingly be adapted.

[0067] The above described examples are not to be understood asrestricting the present invention, because the present invention isdefined by the appended claims. Reference numerals in the claims are notto be understood as restrictions and only serve to make the claimseasier to understand.

1. A digital line driver circuit (1) for driving a transmission line,having a signal input to receive a digital input signal (Di, Dib) and asignal output for outputting a digital output signal in accordance withsaid digital input signal (Di, Dib), said digital line driver circuit(1) being adapted to provide a pre-distortion operating mode in whichmode said digital output signal (Di, Dib) is provided withpre-distortion, and an operating mode without pre-distortion, inaccordance with a mode selection signal; the digital line driver circuit(1) comprising a signal processing section (2) arranged to receive saiddigital input signal (Di, Dib) and said mode selection signal and tooutput one or more control signals (S2; A, B, C, D) that depend on saiddigital input signal (Di, Dib) and on said mode selection signal; anoutput stage (3) arranged to receive said one or more control signals(S2; A, B, C, D) and to output said output signal (OUTP, OUTN) independence on said one or more control signals; wherein said outputstage (3) comprises a reference signal generating section (31) arrangedto generate m distinctive reference signal levels (S32; Vph, Vrh, Vrl,Vpl), m being an integer larger than two, and a signal switching section(32) arranged to receive said one or more control signals (S2; A, B, C,D) and said reference signal levels (S32; Vph, Vrh, Vrl, Vpl) output bysaid reference signal generating section (31), and arranged to selectamong said reference signal levels for coupling with said signal outputin accordance with said one or more control signals, in order togenerate and output said output signal (OUTP, OUTN).
 2. A digital linedriver circuit (1) according to claim 1, wherein said digital inputsignal (Di, Dib) has n signal levels, n being an integer larger than 1,and said digital output signal (OUTP, OUTN) has n signal levels in saidfirst mode and m signal levels in said second mode, where m is aninteger larger than n.
 3. The digital line driver circuit (1) of claim 1or 2, comprising a delay circuit (21) arranged to delay said digitalinput signal (Di, Dib) by a predetermined delay amount (ΔT) and tooutput a corresponding delayed signal (Dd, Ddb), and a gate sectioncomprising a plurality of gates (23,24, 25, 26, 27, 28, 29, 30) forreceiving and processing said digital input signal (Di, Dib) and saiddelayed signal (Dd, Ddb), and being arranged to generate said one ormore control signals (S2; A, B, C, D).
 4. The digital line drivercircuit (1) of claim 3, wherein said gate section is arranged to alsoreceive said mode selection signal (Pe).
 5. The digital line drivercircuit (1) according to any one of the preceding claims, wherein saidreference signal generating section comprises a reference voltageproviding section (310) arranged to output a plurality of referencevoltages (S31; Vrph, Vrrh, Vrrl, Vrpl), and an impedance conversionsection (311) comprising a plurality of impedance conversion circuitsarranged to receive said plurality of reference voltages (S31; Vrph,Vrrh, Vrrl, Vrpl) and to generate said m signals (S32; Vph, Vrh, Vrl,Vpl) in response thereto.
 6. The digital line driver circuit (1)according to any one of the preceding claims, furthermore comprising acurrent balancing section (312) arranged to receive said one or morecontrol signals (S2; A, B, C, D) and to generate currents in accordancetherewith in order to balance a supply current of said digital linedriver circuit (1).
 7. The digital line driver circuit (1) of claim 6,wherein said current balancing section (312) comprises switching devices(3121, 3122, 3123) controlled in dependence on said one or more controlsignals (S2; A, B, C, D) and arranged to selectively provide connectionsbetween predetermined outputs of said impedance conversion circuits(3111, 3112, 3113, 3114), said connections having predeterminedimpedance values (Rpr, Rpp).
 8. The digital line driver circuit (1) ofclaim 7, wherein said switching devices (3121, 3122, 3123) comprise MOStransistors that also provide said impedance values (Rpr, Rpp).
 9. Thedigital line driver circuit according to any one of the claims 5 to 8,wherein each of said impedance conversion circuits comprises anoperational amplifier circuit (3111, 3112, 3113, 3114) having a pushpull output stage.
 10. A method for operating a digital line drivercircuit (1) that is arranged to receive a digital input signal (Di, Dib)and to output a digital output signal (OUTP, OUTN) in accordance withsaid digital input signal (Di, Dib), comprising operating said digitalline driver circuit (1) in at least a first and a second mode inaccordance with a mode selection signal (Pe), wherein said first mode isa signal relay mode in which said digital output signal (OUTP, OUTN)follows said digital input signal (Di, Dib), and said second mode is apre-distortion mode in which said digital output signal (OUTP, OUTN)follows said digital input signal (Di, Dib) and has an additionalpredetermined distortion; receiving said digital input signal (Di, Dib)and said mode selection signal and outputting one or more controlsignals (S2; A, B, C, D) that depend on said digital input signal (Di,Dib) and on said mode selection signal; processing said one or morecontrol signals (S2; A, B, C, D) to output said output signal (OUTP,OUTN) in dependence on said one or more control signals; wherein saidprocessing step comprises generating m distinctive reference signallevels (S32; Vph, Vrh, Vrl, Vpl), m being an integer larger than two,and selecting among said reference signal levels for coupling with saidsignal output in accordance with said one or more control signals (S2;A, B, C, D), in order to generate and output said output signal (OUTP,OUTN).